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Tanner EDA to Preview HiPer Simulation A/MS and Participate in Panel on Analog Productivity at DATE 2012

MONROVIA, California – March 6, 2012 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), will preview HiPer Simulation A/MS and participate in a panel on analog productivity at the Design, Automation and Test in Europe conference (DATE 2012).  HiPer Simulation A/MS is a mixed-signal electronic design automation (EDA) tool suite that integrates Tanner EDA’s analog design, layout and physical verification tools with third-party logic synthesis and mixed-language VHDL and Verilog simulation. DATE 2012 takes place from 12-16 March in Dresden, Germany.

PANEL:

What: Panel entitled “Analog Productivity – Design and Test of Analog/Mixed Signal ASICs” chaired by Prof. Georges Gielen, Head of Department of Electrical Engineering (ESAT),  Katholieke Universiteit Leuven, Belgium.

Abstract: With analog an ever-important aspect of emerging microelectronic applications, never has the need to improve productivity been more acute. Drawing from a range of industry experts, this panel will highlight and discuss the main areas affecting this field, namely analog/digital co-design, IP reuse, layout automation and design for test/yield.

Who:

  • Jeff Miller, Director of Product Management, Tanner EDA, USA / System-level simulation   
  • Ciaran Whyte, CTO, IC Mask Design Limited, Ireland / Layout acceleration
  • Dr. Holger Haberla, Non-Volatile Memory Design Manager, X-FAB Semiconductor Foundries AG, Germany / IP reuse            
  • Marc Hutner, DFT Architecture Engineering, Teradyne, USA/ Design for test, yield

When: Tuesday, 13March from 13:15 – 14:15

Where: Exhibition Theatre

DEMONSTRATIONS:

What: Preview of HiPer Simulation A/MS, an integrated solution that gives designers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification, logic synthesis and mixed VHDL and Verilog simulation. HiPer Simulation A/MS will combine industry-leading technologies into a highly productive design flow for mixed-signal design with industry-leading price-performance.

When:  Tuesday, March 13th through Thursday, March 15th, 2012

Where: Tanner EDA Booth #37

About Tanner EDA

Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

 

HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc.

All other trademarks and trade names are the property of their respective owners.

 

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Media Contact :

Linda Marchant, Cayenne Communication, 919-451-0776, This email address is being protected from spambots. You need JavaScript enabled to view it.

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