Tanner EDA Unveils HiPer Silicon v16 with Open Access at DAC 2011
EDA engineers and customers give presentations, participate in exhibitor forums and pavilion panel for analog IC and MEMS designers
MONROVIA, California â€“ May 25, 2011 -- Â At DAC 2011, Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), will demonstrate a special pre-release version of their full-flow tool suite for analog IC and MEMS designers, HiPer Silicon v16. The company will also be presenting two exhibitor forums, participating in a panel on analog process design kits (PDKs), and sponsoring the 5th annual IPL luncheon. The 48th Design Automation Conference (DAC) will be held at the San Diego Convention Center in San Diego, California, from June 5-10, 2011.
Tanner EDA in Booth #2231:
Â Â Â Â HiPer Silicon v16 builds on Tanner EDAâ€™s 23-year legacy of providing industry-leading price-performance and interoperability. V16 will include full Open Access database compatibility for layout, enabling designers to share files with colleagues and business partners using Si2 database standards. Larger design teams will appreciate the enhanced collaborative design capability â€“ powered by Open Access.
Â Â Â Â Anyone viewing a product demonstration can enter into a drawing to win an Apple iPad, iPod touch, or other prizes. Click here to schedule a demo at DAC -- http://www.tannereda.com/dac2011
Â Â Â Â Tanner EDA also is hosting a schedule of presentations by foundry partners, customers, and Tanner EDA engineers in the booth.
Demonstrations: Monday, June 6 through Wednesday, June 8, 2011 from 9:00am â€“ 6:00pm
In-booth presentations by customers: http://www.tannereda.com/dac2011
Daily raffle drawings: Monday, Tuesday and Wednesday at 10:00 am, 1:00 pm and 4:00 pm. Entrants must be present to win.
Exhibitor Forums: Monday, June 6, 2011
Location: Exhibit Hall G, Booth #1005
10:40 - 11:15 am: Analog IC Design - Why a Cohesive Tool Flow Drives Productivity
Abstract: As analog IC designers strive to keep pace with the rapidly increasing market demands around quicker time-to-market, productivity has become a mandate. This presentation will discuss the productivity advantages afforded by using a cohesive analog design tool suite comprised of schematic capture, simulation, layout, and physical verification. Findings from a recent survey of analog IC designers -- touching on the key benefits and challenges they see with using a full-flow design suite -- will be presented and discussed.
Speakers: Mass Sivilotti, Chief Scientist, Tanner EDA / John Zuk, VP Marketing & Strategy, Tanner EDA (Both from Monrovia, California)
3:00 - 3:35 pm: Analog IC Design at the Edge: A New Twist for Nanoscale Productivity
Abstract: Nanoscale analog IC design productivity is a major concern as chip device counts approach 1 billion at 32 nm. A multitude of physical device pattern separation dimensions must now be entered into the pre-layout simulation models to accurately predict post-layout circuit performance. The Tanner EDA approach -- based on the seminal work of Mead and Conway -- offers a novel method that enables rapid circuit simulation in a multitude of nanoscale technology nodes and platform options. As a result, pre-layout simulation accuracy is improved, having a direct impact on increasing analog IC manufacturing yields while simultaneously increasing design productivity.
Speakers: Dr. Lanny Lewyn, President, Lewyn Consulting, Laguna Beach, California / Nicolas Williams, Director of Product Management, Tanner EDA, Monrovia, California
IPL Luncheon: Monday, June 6, 2011
Location:Â San Diego Marriott, Marina Ballroom D-E
12:00 â€“ 1:30 pm: Interoperable PDK standards are Here to Stay: New Era of Analog/Custom Innovation
Summary: At the 5th annual IPL Luncheon, the IPL Alliance will present an update on the current and future success of IPL standards. Attendees will hear about how the industry is embracing the IPL 1.0 standard, specs of the new interoperable design constraint standard, and collaboration among standards (How oPDK and iPDK will work together).
Pavilion Panel - Wednesday, June 8, 2011
Location: Booth #3421
11:15am - 12:00pm: Why the Delay in Analog PDK?
Summary: Why does it take so long for foundries to release analog/mixed-signal process design kits (PDKs)? The amount of A/MS content in designs is growing and the pressure to move to smaller process nodes is increasing. This panel provides an opportunity to talk to the people who develop PDKs and reference flows.
Moderator: Steven Klass, Analog Mixed-Signal Design Automation Expert
Speakers: Mass Sivilotti, Tanner EDA, Monrovia, CA/ Tom Quan, Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA / Ofer Tamir, TowerJazz, Newport Beach, CA
For the latest news about Tanner EDA at DAC 2011, see http://www.tannereda.com/dac2011
Tanner EDA provides a complete line of software solutions that drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.
Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.
HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc.
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